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Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS (in English)
Krishnendu Chakrabarty
(Author)
·
Brandon Noia
(Author)
·
Springer
· Paperback
Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS (in English) - Noia, Brandon ; Chakrabarty, Krishnendu
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Origin: United Kingdom
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Synopsis "Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS (in English)"
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
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All books in our catalog are Original.
The book is written in English.
The binding of this edition is Paperback.
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